ERC-IIITH / ERC-IIITH/Verilog-Library
Gates
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good first issue
- 主要语言
- Verilog
- 星标
- 4
- 派生
- 11
- PR 合并指标
- 30 天内没有已合并 PR
描述
2 input AND, OR, NAND, NOR, XOR and XNOR gates and NOT gate
RTL model using operators and structural model using gate primitives
File structure example
> nand
>> nand_struct.v
nand_struct_tb.v
nand_rtl.v
nand_rtl_tb.v
where `_struct` is for the structural model and `_rtl` for the RTL model
This issue can be broken down and solved in multiple PRs.
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