lowRISC/gsoc-sim-mem
View on GitHubA simulated memory controller for use in FPGA designs that want to model real system performance
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- 1
- Dominant language
- SystemVerilog
- License
- Apache-2.0
- Last GitHub push
- Apr 19, 2021
- Latest indexed
- Sep 19, 2026
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- Contributing guide
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Difficulty 4/5 3-5 days Newbie friendliness 30/100
lowRISC/gsoc-sim-mem#18 ·