Response ready signals not detected in Xilinx Vivado

When using Xilinx Vivado as described in vivado_integration.md, the output ready (s_rready and s_bready) signals are not detected.

I replayed the same transactions in a cycle accurate manual simmem_top_tb.cc testbench and could not reproduce the issue in this controlled environment.
Therefore, I suspect either the Verilog wrapper or to the integration process that I described in vivado_integration.md to be the cause.

Start by reading vivado_integration.md and comparing the Vivado setup with the cycle-accurate simmem_top_tb.cc testbench, where the issue was not reproduced. Then inspect the Verilog wrapper and integration process for how s_rready and s_bready are exposed and detected. Done means those response-ready signals are reliably detected when using Xilinx Vivado.

Written by the indexing model from the issue text.