Owner
jeanthom
11 indexed repositories · View on GitHub
-
stlink-tool
Firmware uploader for ST-Link
C · 70 stars
-
openocd-dirtyjtag
OpenOCD fork with DirtyJTAG support (WIP)
C · 22 stars
-
Enigma
Jar reverse engineering tool
Java · 19 stars
-
gram
DDR3 controller for nMigen (WIP)
Python · 14 stars
-
jtaginabox
JTAG in a box : easy JTAG for router flashing, recovery and many more use cases !
C · 13 stars
-
Otter-Iron-PRO-BOM
LCSC+Arrow BOM for Otter Iron PRO v2
HTML · 13 stars
-
ibugger
Tools for tinkering with iPods by TheSeven
Assembly · 7 stars
-
NEX1stGenRE
Sony NEX (1st gen) reverse engineering
6 stars
-
usb2sniffer-cli
CLI application for LambdaConcept's USB2Sniffer
C · 5 stars
-
chubby75-blinken
My first LiteX project
Python · 0 stars
-
learnvhdl
Learn VHDL from your browser
JavaScript · 0 stars
-
bug
jeanthom/Enigma#2 · 0 comments · 0 reactions · 0 assignees ·
-
Gradle Build Crashed Open
jeanthom/Enigma#3 · 0 comments · 0 reactions · 0 assignees ·
-
nex 5 Open
jeanthom/NEX1stGenRE#1 · 0 comments · 0 reactions · 0 assignees ·
-
bug
jeanthom/jtaginabox#1 · 23 comments · 0 reactions · 0 assignees ·
-
jeanthom/chubby75-blinken#1 · 0 comments · 0 reactions · 0 assignees ·
-
jeanthom/Otter-Iron-PRO-BOM#1 · 3 comments · 0 reactions · 0 assignees ·
-
jeanthom/Otter-Iron-PRO-BOM#2 · 2 comments · 0 reactions · 0 assignees ·
-
Capacitor is too big Open
jeanthom/Otter-Iron-PRO-BOM#4 · 0 comments · 0 reactions · 0 assignees ·
-
bug
jeanthom/Otter-Iron-PRO-BOM#7 · 6 comments · 0 reactions · 0 assignees ·
-
jeanthom/learnvhdl#3 · 0 comments · 0 reactions · 0 assignees ·
-
jeanthom/learnvhdl#4 · 0 comments · 0 reactions · 0 assignees ·
-
jeanthom/learnvhdl#6 · 0 comments · 0 reactions · 0 assignees ·
-
jeanthom/learnvhdl#8 · 0 comments · 0 reactions · 0 assignees ·
-
jeanthom/ibugger#3 · 7 comments · 0 reactions · 0 assignees ·
-
Error usb timeout Open
jeanthom/ibugger#4 · 0 comments · 0 reactions · 0 assignees ·
-
Progress Open
jeanthom/openocd-dirtyjtag#1 · 0 comments · 0 reactions · 0 assignees ·
-
IR capture errors Open
jeanthom/openocd-dirtyjtag#2 · 8 comments · 0 reactions · 0 assignees ·
-
jeanthom/openocd-dirtyjtag#3 · 14 comments · 2 reactions · 0 assignees ·
-
compile error: ‘status’ may be used uninitialized in this function [-Werror=maybe-uninitialized] Open
jeanthom/openocd-dirtyjtag#5 · 1 comment · 0 reactions · 0 assignees ·
-
jeanthom/openocd-dirtyjtag#6 · 7 comments · 0 reactions · 0 assignees ·
-
НЕ СОБИРАЕТСЯ Open
jeanthom/openocd-dirtyjtag#9 · 0 comments · 0 reactions · 0 assignees ·
-
enhancement
-
enhancement libgram
-
AXI frontend Openaxi enhancement interface
-
ecp5 enhancement testing
-
bug core help wanted phy
jeanthom/gram#39 · 14 comments · 0 reactions · 0 assignees ·
-
enhancement interface wishbone
-
question
-
Publish gram on PyPI Openenhancement packaging
-
ecp5 enhancement phy
-
bug core testing
-
ecp5 enhancement phy
-
ST-LinkV2/1 Open
jeanthom/stlink-tool#9 · 1 comment · 0 reactions · 0 assignees ·
-
jeanthom/stlink-tool#14 · 13 comments · 0 reactions · 0 assignees ·
-
jeanthom/stlink-tool#15 · 2 comments · 0 reactions · 0 assignees ·
-
High RAM usage Open
jeanthom/usb2sniffer-cli#1 · 0 comments · 0 reactions · 0 assignees ·
-
libusb support Open
jeanthom/usb2sniffer-cli#4 · 3 comments · 0 reactions · 0 assignees ·