Bring back testing in gram
Open
enhancement
- Dominant language
- Python
- Stars
- 14
- Forks
- 1
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- No merged PRs in 30d
Description
During the LiteDRAM -> dram I ditched all the simulation/test files. This is quite problematic, and should be addressed ASAP.
Ideas:
* Formal verification whenever possible
* Use SV models ([Micron offers one](https://github.com/tej-chavan/Design-and-Verification-of-DDR3-Memory-Controller/blob/master/memory_model/ddr3.sv))
* HowTo SV with FOSS tools? HowTo DDR I/O modeling for the ECP5?
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