SystemVerilog interface related broad issue

The `tcb_gpio.sv` RTL is a simple GPIO peripheral with `tcb_if.sv` SystemVerilog interface as the system bus.
`tcb_gpio_wrap.sv` is just a wrapper providing simple signals for ports.

The design was tested in Vivado and consumed the expected 96 FFs.

The issues are:
1. `tcb_gpio` module is apparently removed.
2. Please explain warnings like `Warning: Identifier `\bus.vld' is implicitly declared.`
3. `Warning: wire '\bus.rdt' is assigned in a block at tcb_gpio.sv:56.0-56.0.` is incorrect, since there are no wires in the design, all signals are of type `logic`.
4. `ERROR: Failed to resolve identifier \bus.adr for width detection!`

A few comments:
- The signal `trn = vld & rdy` is defined as RTL inside the interface.
- There is some parameter validation code which is just experimental. I am now to it, I do not expect it to work.

To reproduce this issue do:
```
git clone https://github.com/jeras/UHDM-tests
cd UHDM-tests
../yosys-uhdm-plugin-integration/image/bin/yosys -s build_gpio.tcl
```

This is my output:
```
$ ../rp32/submodules/yosys-uhdm-plugin-integration/image/bin/yosys -s build_gpio.tcl

/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/

Yosys 0.16+65 (git sha1 52d8ddee0, gcc 9.4.0-1ubuntu1~20.04.1 -fPIC -Os)

-- Executing script file `build_gpio.tcl' --

1. Executing Verilog with UHDM frontend.
[INF:CM0023] Creating log file ./slpp_all/surelog.log.

[WRN:PA0205] tcb_if.sv:19:1: No timescale set for "tcb_if".

[WRN:PA0205] tcb_gpio.sv:23:1: No timescale set for "tcb_gpio".

[WRN:PA0205] tcb_gpio_wrap.sv:19:1: No timescale set for "tcb_gpio_wrap".

[INF:CP0300] Compilation...

[INF:CP0303] tcb_gpio.sv:23:1: Compile module "work@tcb_gpio".

[INF:CP0303] tcb_gpio_wrap.sv:19:1: Compile module "work@tcb_gpio_wrap".

[INF:CP0304] tcb_if.sv:19:1: Compile interface "work@tcb_if".

[INF:CP0302] Compile class "work@mailbox".

[INF:CP0302] Compile class "work@process".

[INF:CP0302] Compile class "work@semaphore".

[INF:EL0526] Design Elaboration...

[INF:CP0335] tcb_if.sv:57:8: Compile generate block "work@tcb_gpio_wrap.bus.gen_dly".

[INF:CP0335] tcb_if.sv:58:5: Compile generate block "work@tcb_gpio_wrap.bus.gen_dly.gen_rsp".

[NTE:EL0503] tcb_gpio_wrap.sv:19:1: Top level module "work@tcb_gpio_wrap".

[NTE:EL0508] Nb Top level modules: 1.

[NTE:EL0509] Max instance depth: 2.

[NTE:EL0510] Nb instances: 2.

[NTE:EL0511] Nb leaf instances: 0.

[INF:UH0706] Creating UHDM Model...

[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 0
[WARNING] : 3
[ NOTE] : 5
Warning: Removing unused module: \tcb_gpio from the design.
Generating RTLIL representation for module `\tcb_gpio_wrap'.
tcb_gpio_wrap.sv:51: Warning: Identifier `\bus.vld' is implicitly declared.
tcb_gpio_wrap.sv:52: Warning: Identifier `\bus.wen' is implicitly declared.
tcb_gpio_wrap.sv:53: Warning: Identifier `\bus.adr' is implicitly declared.
tcb_gpio_wrap.sv:54: Warning: Identifier `\bus.ben' is implicitly declared.
tcb_gpio_wrap.sv:55: Warning: Identifier `\bus.wdt' is implicitly declared.
tcb_gpio_wrap.sv:57: Warning: Identifier `\bus.rdt' is implicitly declared.
tcb_gpio_wrap.sv:58: Warning: Identifier `\bus.err' is implicitly declared.
tcb_gpio_wrap.sv:59: Warning: Identifier `\bus.rdy' is implicitly declared.
Generating RTLIL representation for module `$paramod\tcb_gpio\GW=32'd32'.
Warning: wire '\bus.rdt' is assigned in a block at tcb_gpio.sv:56.0-56.0.
tcb_gpio.sv:59: ERROR: Failed to resolve identifier \bus.adr for width detection!
```

Start by running the issue's build_gpio.tcl reproduction in the UHDM-tests checkout, then inspect tcb_if.sv, tcb_gpio.sv, and tcb_gpio_wrap.sv alongside the reported output. Trace why tcb_gpio is removed and why bus members are implicitly declared or unresolved. Done means the reported module, interface, wire, and identifier diagnostics are explained or corrected and the reproduction output is checked again.

Written by the indexing model from the issue text.