chipsalliance / chipsalliance/synlig
unpacked array initialization with assignment pattern
Open
- Dominant language
- Verilog
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Description
I tried to write an initialized memory.
```
// register file (FPGA would initialize it to all zeros)
logic [XLEN-1:0] gpr [0:2**AW-1] = '{default: '0};
```
The error does not provide any details indicating where is the offending code:
```
ERROR: Couldn't find ancestor for tagged pattern!
```
I removed the initialization now, since it does not affect the implementation much, initialization is usually done by SW on ASIC.
This code was only tested with Verilator.
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