Structure parameter element used as as condition in ?: operator ...

Structure parameter element is used as as condition in ?: operator to parameterize an instance.
```
.AW (ISA.spec.base.E ? 4 : 5),
```
The `AW` parameter is defined as:
```
int unsigned AW = 5, // can be 4 for RV32E base ISA
```
The reported error is:
```
../../../hdl/rtl/core/r5p_core.sv:333: ERROR: Identifier `\ISA' is implicitly declared and `default_nettype is set to none.
```

This code works properly in Verilator, Vivado synthesis and Quartus.

This is not a critical issue for me, since I have only one instance, and it was trivial to workaround.

Start with hdl/rtl/core/r5p_core.sv at line 333 and reproduce the diagnostic for the conditional parameter expression using the shown AW and ISA values. Compare the behavior with the reported Verilator, Vivado, and Quartus results; done means Synlig no longer treats the structure parameter reference as an implicit identifier while retaining correct parameterization.

Written by the indexing model from the issue text.