chipsalliance / chipsalliance/synlig
Inconclusive Equivalence
Open
formal verification
- Dominant language
- Verilog
- Stars
- 237
- Forks
- 29
- PR merge metrics
- No merged PRs in 30d
Description
Opened this case:
https://github.com/YosysHQ/yosys/issues/3428
Contributor guide
No contributing guide indexed for this repository
Research direction
Start by reading the linked Yosys issue #3428 and determine how it relates to Synlig's inconclusive equivalence case. The issue provides no Synlig file, test, reproduction, or acceptance criteria, so first identify the affected entry point and a way to reproduce the result; done would require a defined resolution for that case.
Written by the indexing model from the issue text.
Assessment
- Domain
- compilers
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 15/100