chipsalliance / chipsalliance/synlig
Segmentation Fault
- Dominant language
- Verilog
- Stars
- 237
- Forks
- 29
- PR merge metrics
- No merged PRs in 30d
Description
I use the latest uhdm to run this orv64 code and encounter segementation fault without more information
This is the test case [https://github.com/hello-eternity/test_orv64_uhdm/tree/main](https://github.com/hello-eternity/test_orv64_uhdm/tree/main)
In the Makefile.in , $(TEST_DIR) need to point to the correct location. Mine is
`/root/yosys-uhdm-plugin-integration/UHDM-integration-tests/tests`
Contributor guide
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Research direction
Start with the linked test_orv64_uhdm test case and its Makefile.in, setting TEST_DIR to the UHDM-integration-tests/tests location described in the issue. Run the case to reproduce the segmentation fault, then trace the failing synthesis path. Done means the supplied case no longer crashes without information and its result can be verified.
Written by the indexing model from the issue text.
Assessment
- Domain
- compilers
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100