chipsalliance / chipsalliance/synlig

Encountered unhandled object '' of type 'break_stmt'

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Dominant language
Verilog
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Description

I got an error like the title. The detailed error information is like this
`ERROR: /root/yosys-uhdm-plugin-integration/UHDM-integration-tests/tests/orv64/rtl/common/pygmy_func.sv:24: Encountered unhandled object '' of type 'break_stmt'`
The source code is :
```
for (int i=0; i<8; i++) begin
if (~way_valid[i] & way_enable[i]) begin
has_empty_way = '1;
replace_way_id = i;
break;
end
end

```
I can only sovle this by change the for-loop logic
This is the test case [https://github.com/hello-eternity/test_orv64_uhdm](https://github.com/hello-eternity/test_orv64_uhdm)
In the Makefile.in , $(TEST_DIR) need to
point to the correct location. Mine is `/root/yosys-uhdm-plugin-integration/UHDM-integration-tests/tests`
This error need replace this file `orv64/rtl/common/pygmy_func copy.sv` into `orv64/rtl/common/pygmy_func.sv`

Contributor guide

No contributing guide indexed for this repository

Research direction

Reproduce the error with the test_orv64_uhdm case, setting TEST_DIR in Makefile.in to the UHDM-integration-tests/tests location. Start with orv64/rtl/common/pygmy_func.sv and compare it with pygmy_func copy.sv, then trace the reported break_stmt handling. Done means the for-loop example no longer reports an unhandled object.

Written by the indexing model from the issue text.

Assessment

Domain
compilers
Issue type
Bug
Difficulty
3/5
Estimated time
1-2 days
Activity status
Quiet
Clarity
Mostly clear
Newbie friendliness
48/100

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