how to report issues

I would like to compile my SV code with yosys+UHDM, I followed the instructions from here:
https://antmicro.com/blog/2022/02/simplifying-open-source-sv-synthesis-with-the-yosys-uhdm-plugin/
except I compiled the latest `yosys` master myself and installed it.

With the first source file I tried I got an error, the second file went well and the third failed again, the code was already tested in Quartus and Vivvado. Now I am not sure how to proceed.

1. Is it ok if I used the script from the antmicro blog to install the plugin, or should I compile it from sources.
2. Is is ok to use the `yosys` master, or should I use a branch/tag/hash?
3. Does it make sense for me to report specific issues or is the project not there yet, and it would be better for me to wait.

I already created an issue here about 2 months ago:
https://github.com/chipsalliance/UHDM-integration-tests/issues/670
Are this tests also running the yosys with the plugin?
I can update this tests with my latest code.
From the log it seems there were fewer issues then, than I have now.
https://github.com/chipsalliance/Surelog/blob/master/third_party/tests/Rp32/rp32.log

I would try to get through more issues myself, but this projects is changing so fast I am not sure which git repo and instructions to look into. Also I lack experience with yosys and the opensource FPGA toolchain, so I will try to get through some examples before adding an extra layer of unknowns due to systemverilog.

Running script:
https://github.com/jeras/rp32/blob/master/fpga/Xilinx/yosys/test.tcl
failing on file/line:
https://github.com/jeras/rp32/blob/master/hdl/rtl/riscv/riscv_isa_pkg.sv#L150
```
Yosys 0.16+41 (git sha1 UNKNOWN, gcc 11.2.0-7ubuntu2 -fPIC -Os)

-- Executing script file `test.tcl' --

1. Executing Verilog with UHDM frontend.
[INF:CM0023] Creating log file ./slpp_all/surelog.log.

[WRN:PA0205] ../../../hdl/rtl/riscv/riscv_isa_pkg.sv:19: No timescale set for "riscv_isa_pkg".

[INF:CP0300] Compilation...

[INF:CP0301] ../../../hdl/rtl/riscv/riscv_isa_pkg.sv:19: Compile package "riscv_isa_pkg".

[INF:CP0302] Compile class "work@mailbox".

[INF:CP0302] Compile class "work@process".

[INF:CP0302] Compile class "work@semaphore".

[INF:EL0526] Design Elaboration...

[NTE:EL0508] Nb Top level modules: 0.

[NTE:EL0509] Max instance depth: 0.

[NTE:EL0510] Nb instances: 0.

[NTE:EL0511] Nb leaf instances: 0.

[INF:UH0706] Creating UHDM Model...

[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 0
[WARNING] : 1
[ NOTE] : 4
ERROR: ../../../hdl/rtl/riscv/riscv_isa_pkg.sv:150: Encountered unhandled operation type 69
```

Start with fpga/Xilinx/yosys/test.tcl and reproduce the failure at hdl/rtl/riscv/riscv_isa_pkg.sv:150, recording the Yosys, UHDM plugin, and source versions. Compare the setup with the referenced integration test issue and rp32.log. Done means isolating a specific reproducible failure or determining the correct repository, version, and test details for a focused report.

Written by the indexing model from the issue text.