ERROR: 2nd expression of procedural for-loop is not constant!

As the title error
I would like to translate the sv code of orv64 into verilog code and use yosys to synthesis .[orv64](https://gitlab.com/picorio/OpenSource/hardware/orv64)
`/root/yosys-uhdm-plugin-integration/UHDM-integration-tests/tests/orv64_uhdm/rtl/../rtl/orv64/orv64_ptw_core.sv:224: ERROR: 2nd expression of procedural for-loop is not constant!
make: *** [Makefile:55: uhdm/yosys/test-ast] Error 1`
the code is just like this
I think this is caused by insufficient uhdm support, so I can only manually split this for loop into a constant for loop and an if conditional statement

Here is a case
(almost 30MB, so I split it into two files and I think you should rename the orv64_1.zip to orv64_uhdm.z01 before unzip)
[orv64_1.zip](https://github.com/antmicro/yosys-uhdm-plugin-integration/files/8311378/orv64_1.zip)
[orv64_uhdm.zip](https://github.com/antmicro/yosys-uhdm-plugin-integration/files/8311380/orv64_uhdm.zip)

Start with the failing loop at orv64_ptw_core.sv:224 and reproduce it using the provided orv64_uhdm case and Makefile target at line 55. Trace how the synthesis tool handles the loop's second expression, then verify that the case translates without the constant-expression error.

Written by the indexing model from the issue text.