Potential targets for Yosys-based CI

Some active projects that could be interested in having a Yosys-based CI flow (similar to what we have in Ibex/Opentitan):
- SERV/Servant SoC
- https://github.com/olofk/serv
- Supported by UHDM/Verilator, targets Arty A7 35T.

- OpenHWGroup cores
- https://github.com/openhwgroup/core-v-mcu
- Already using fusesoc, Verilator, Verible. Targets Nexys-A7-100T.

- Snitch core
- https://github.com/pulp-platform/snitch
- Uses Verilator, Verible for linting.

- IOb-SoC
- https://github.com/IObundle/iob-soc
- Uses Icarus, but relies on custom VM for tooling, maybe would be interested in open synthesis flow?

Review the existing Yosys-based CI flow in Ibex/OpenTitan, then examine the listed SERV/Servant SoC, OpenHWGroup cores, Snitch, and IOb-SoC projects. Determine which project has a defined integration path and what CI scope and completion criteria would be required; the issue currently provides candidates but no specific implementation target.

Written by the indexing model from the issue text.