Port is connected to constants: { $auto$hierarchy.cc:1462:execute$1 1'0 }

Executing HIERARCHY pass of the following module results in an error: `Output port b.a_inst.a1 (a) is connected to constants: { $auto$hierarchy.cc:1462:execute$1 1'0 }`
```SystemVerilog
module a (output logic [4:2] a1, output logic a2);
endmodule: a

module b (output logic b1);

a a_inst(.a1(b2), .a2(b1));

assign b2 = 'b0;

endmodule: b
```

Command: `synlig -f systemverilog -o output.blif -S test.sv `

### Expected Behavior
The hierarchy pass must complete successfully, or a human-readable error should be thrown (should `$auto$hierarchy.cc:1462:execute$` be a part of the error message?)

This issue occurs in `Synlig (git sha1 2d838edc9, c++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)`

Found by a [verilog model](https://github.com/DepTyCheck/verilog-model) using [deptycheck](https://github.com/buzden/deptycheck)

Reproduce the failure with the supplied SystemVerilog module and the synlig HIERARCHY command. Trace how the HIERARCHY pass handles output port b.a_inst.a1 when it is connected to a constant. Done means the pass completes successfully or reports a human-readable error without exposing the generated internal location.

Written by the indexing model from the issue text.