Getting Assert `inst failed in /systemverilog/uhdm_ast.cc

Hello,

I am building my SystemVerilog code with synlig and when yosys goes to create the UHDM model and I get an error. I am getting the following output before the ERROR:

[NTE:EL0503] /mnt/c/projects/SV_2/rtl_vlog/top/top.sv:20:1: Top level module "work@top".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 8.
[NTE:EL0510] Nb instances: 1170.
[NTE:EL0511] Nb leaf instances: 297.
[INF:UH0706] Creating UHDM Model...
[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 0
[WARNING] : 0
[ NOTE] : 5
ERROR: Assert `inst' failed in /mnt/c/projects/github/synlig-main/frontends/systemverilog/uhdm_ast.cc:2739.

I am using the following commands to load the files:
plugin -i systemverilog
... (Use same include files and package file in all the file calls)
read_systemverilog -defer ../rtl_vlog/defs/register_defs.sv ../rtl_vlog/defs/defs.sv ../rtl_vlog/defs/RTL_asic_synth_pkg.sv ../rtl_vlog/top/top.sv
read_systemverilog -link

Apologies if I have not included all the information you require as I am a new user to synlig.

Thanks

Reproduce the assertion using the listed plugin, read_systemverilog -defer, and read_systemverilog -link commands, then inspect frontends/systemverilog/uhdm_ast.cc around line 2739. Identify which instance or input causes the failed assertion and define a regression case; done means the reported design no longer aborts there and the relevant behavior is covered by a test.

Written by the indexing model from the issue text.