chipsalliance / chipsalliance/synlig
fsm_encoding attribute is not passed to Yosys
- Dominant language
- Verilog
- Stars
- 237
- Forks
- 29
- PR merge metrics
- No merged PRs in 30d
Description
I am using e97602e68e55273fa11564fbb4388b119c18eeb3
with Yosys `Yosys 0.34+43 (git sha1 d21c464ae, c++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)`
Looks like the following attribute is not passed to Yosys. `(* fsm_encoding="user" *) state_t curr_state ; ` The following example (RTL+Yosys script) illustrates the issue https://drive.google.com/file/d/1227_ul1Q_E0YteFAvkZ7HTWQ5CoVVe7A/view?usp=drive_link
Just change the pointer to the Yosys binary and run `make kiss`. There is no `attribute \fsm_encoding "user"` listed in the output.
Contributor guide
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Research direction
Start with the linked RTL and Yosys script, update the Yosys binary pointer, and run `make kiss` to reproduce the missing `fsm_encoding` attribute. Compare the generated output with the expected `attribute \fsm_encoding "user"` and trace the integration path that forwards RTL attributes to Yosys; done means the attribute appears in the output.
Written by the indexing model from the issue text.
Assessment
- Domain
- compilers, tooling
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 52/100