chipsalliance / chipsalliance/synlig

Property index 0 is greater than the number of properties in file (.btor2)

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Dominant language
Verilog
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237
Forks
29
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No merged PRs in 30d

Description

When I refactored the property:
always @(posedge clk) begin
if (qed_ready) begin
sqed: assert ((mem1 == mem17) && (mem2 == mem18) &&
(mem3 == mem19) && (mem4 == mem20) &&
(mem5 == mem21) && (mem6 == mem22) &&
(mem7 == mem23) && (mem8 == mem24) &&
(mem9 == mem25) && (mem10 == mem26) &&
(mem11 == mem27) && (mem12 == mem28) &&
(mem13 == mem29) && (mem14 == mem30) &&
(mem15 == mem31)
);
end
end
into the following form:
property self_consistency;
@(posedge clk) qed_ready |-> ((mem1 == mem17) && (mem2 == mem18) &&
(mem3 == mem19) && (mem4 == mem20) &&
(mem5 == mem21) && (mem6 == mem22) &&
(mem7 == mem23) && (mem8 == mem24) &&
(mem9 == mem25) && (mem10 == mem26) &&
(mem11 == mem27) && (mem12 == mem28) &&
(mem13 == mem29) && (mem14 == mem30) &&
(mem15 == mem31)
);
endproperty
sqed: assert property (self_consistency);

and attempted to generate a btor2 file, an error occurred during the solving process using Pono.

Contributor guide

No contributing guide indexed for this repository

Research direction

The report names no repository file, test, or entry point. Reproduce the Pono BTOR2-generation failure with the two property forms, then locate the relevant SystemVerilog and BTOR2 handling and add a regression test. Done means the refactored property generates a valid BTOR2 file and solves without the property-index error.

Written by the indexing model from the issue text.

Assessment

Domain
compilers
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
20/100

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