Bug with multidimensional array selection

```systemverilog
module MultiDimHierPath8 (
input logic [3:0] a,
input logic [3:0] b,
output logic [1:0][3:0] out
);
typedef logic [3:0] logic4;

struct packed {
logic4 [2:0] vector3x4;
} s;

assign s.vector3x4[1] = a;
assign s.vector3x4[2] = b;

assign out = s.vector3x4[2:1];

endmodule
```
```verilog
// Generated by Synlig (alaindargelas/synlig, stable_rs, d93afadc)
module MultiDimHierPath8(a, b, out);
input [3:0] a;
wire [3:0] a;
input [3:0] b;
wire [3:0] b;
output [7:0] out;
wire [7:0] out;
wire [11:0] s;
assign out = { 4'h0, b };
assign s[11:4] = { b, a };
endmodule
```
```verilog
// Generated by Cadence Genus(TM) Synthesis Solution 20.11-s111_1
module MultiDimHierPath8(a, b, \out[0] , \out[1] );
input [3:0] a, b;
output [3:0] \out[0] , \out[1] ;
wire [3:0] a, b;
wire [3:0] \out[0] , \out[1] ;
assign \out[1] [0] = b[0];
assign \out[1] [1] = b[1];
assign \out[1] [2] = b[2];
assign \out[1] [3] = b[3];
assign \out[0] [0] = a[0];
assign \out[0] [1] = a[1];
assign \out[0] [2] = a[2];
assign \out[0] [3] = a[3];
endmodule
```

_Originally posted by @sifferman in https://github.com/chipsalliance/synlig/issues/2125#issuecomment-1847548054_

Start with the SystemVerilog reproducer in this issue and run it through Synlig, then compare its generated Verilog with the Cadence Genus output shown here. Trace the multidimensional array selection and packed-struct handling from the relevant synthesis entry point; done means the generated output preserves the selected values for a and b rather than producing only b.

Written by the indexing model from the issue text.