Bug with multidimensional vector inside struct with other vector members

Found an issue with [alaindargelas/synlig@stable_rs](https://github.com/alaindargelas/synlig/tree/stable_rs)

```systemverilog
module MultiDimHierPath7 (
input logic [3:0] a,
input logic [3:0] b,
output logic [1:0][3:0] out
);

struct packed {
logic [1:0] unused1;
logic [1:0][3:0] vector2x4;
logic [1:0] unused0;
} s;

assign s.vector2x4[0] = a;
assign s.vector2x4[1] = b;

assign out = s.vector2x4;

endmodule
```
```verilog
// Generated by Synlig (alaindargelas/synlig, stable_rs, d93afadc)
module MultiDimHierPath7(a, b, out);
input [3:0] a;
wire [3:0] a;
input [3:0] b;
wire [3:0] b;
output [7:0] out;
wire [7:0] out;
wire [11:0] s;
assign out[1:0] = { b[0], a[0] };
assign s[9:2] = { out[7:2], b[0], a[0] };
endmodule
```
```verilog

// Generated by Cadence Genus(TM) Synthesis Solution 20.11-s111_1
module MultiDimHierPath7(a, b, \out[0] , \out[1] );
input [3:0] a, b;
output [3:0] \out[0] , \out[1] ;
wire [3:0] a, b;
wire [3:0] \out[0] , \out[1] ;
assign \out[1] [0] = b[0];
assign \out[1] [1] = b[1];
assign \out[1] [2] = b[2];
assign \out[1] [3] = b[3];
assign \out[0] [0] = a[0];
assign \out[0] [1] = a[1];
assign \out[0] [2] = a[2];
assign \out[0] [3] = a[3];
endmodule
```

_Originally posted by @sifferman in https://github.com/chipsalliance/synlig/issues/2125#issuecomment-1844804775_

Start by reproducing the issue with the MultiDimHierPath7 SystemVerilog example and compare Synlig's generated output with the Cadence Genus output included here. Trace the synthesis handling of packed multidimensional vectors inside structs, and consider the issue done when the generated connections preserve all four bits of both vector members and match the reference behavior.

Written by the indexing model from the issue text.