The anyconst and anyseq attributes are ignored

The parser ignores attributes that are used in formal verification with SymbiYosys (anyseq, anyconst, allseq, allconst). The code shown below passes verification with `read_verilog`, but fails with `read_systemverilog`.

```verilog
module test (input wire clock);

`ifdef FORMAL
(* anyconst *) reg [7:0] x;
reg f_past_valid = 1'b0;

always @(posedge clock) begin
f_past_valid <= 1'b1;
if (f_past_valid) assert($stable(x));
end
`endif

endmodule
```

Dump Verilog AST of `read_verilog`:
```verilog
module test(clock);
input clock;
reg [7:0] x;
reg f_past_valid;
assign x = (* reg = "x" *)/** AST_FCALL **/;
initial
f_past_valid <= 1'b 0;
always @(posedge clock)
begin
f_past_valid <= 1'b 1;
case (|(f_past_valid))
1'b 1:
/** AST_ASSERT **/
endcase
end
endmodule
```

Dump Verilog AST of `read_systemverilog`:
```verilog
module test(clock);
input [0:0] clock;
reg [7:0] x;
reg [0:0] f_past_valid;
initial
f_past_valid <= 1'b 0;
always @(posedge clock)
begin
f_past_valid <= 1'b 1;
case (|(f_past_valid))
1'b 1:
/** AST_ASSERT **/
endcase
end
endmodule
```

Start by reproducing the supplied module with read_verilog and read_systemverilog, then compare their dumped Verilog ASTs. Trace how the anyconst, anyseq, allseq, and allconst attributes are handled during SystemVerilog parsing; done means the read_systemverilog AST preserves the relevant attribute behavior shown by read_verilog.

Written by the indexing model from the issue text.