chipsalliance / chipsalliance/synlig

synlig crashes on initialization when linked statically to Yosys

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Dominant language
Verilog
Stars
237
Forks
29
PR merge metrics
No merged PRs in 30d

Description

If the module is not linked dynamically, there can be an initialization-fiasco type crash when registering the edif modle.

https://github.com/chipsalliance/synlig/commit/5e1a7ccfa23a56639223ad2840fbd15519679cf8#r131191626

Calling that register function at a time the external variable is not initailized yet is problematic. This should probably be deferred.

Contributor guide

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Research direction

Review the linked commit and the EDIF module registration function mentioned in the report. Reproduce initialization with a statically linked Yosys build, then verify that registration no longer accesses an uninitialized external variable and that startup completes successfully.

Written by the indexing model from the issue text.

Assessment

Domain
compilers
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
35/100

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