RISC-V flt.s and flt.d instructions cause IR sanity check failure

### Description

Issue: RISC-V flt.s and flt.d instructions cause IR sanity check failure
Description:
When using PyVEX to lift RISC-V code containing flt.s or flt.d instructions, IR sanity check fails with:
IRStmt.Put.Tmp: tmp and expr do not match
Root Cause:
Missing type conversion in vex/priv/guest_riscv64_toIR.c. The Iop_CmpEQ32 operation returns Ity_I1 (boolean), but the destination temporary variable is declared as Ity_I32.
Affected Instructions:
- flt.s (line 2492-2495)
- flt.d (line 2989-2992)
Fix:
Add unop(Iop_1Uto32, ...) to convert boolean to 32-bit integer, matching the implementation of feq.s and fle.s:
case 0b001: // flt.s / flt.d
assign(irsb, res,
unop(Iop_1Uto32, binop(Iop_CmpEQ32, mkexpr(cmp), mkU32(Ircr_LT))));
break;

### Steps to reproduce the bug

_No response_

### Environment

_No response_

### Additional context

_No response_