Requirements for "last" signalling conflict for Streams with lower complexities and multiple element lanes

## Background

Using https://abs-tudelft.github.io/tydi/specification/physical.html#signals

For N lanes, indexed 0 through N-1:
C < 8: [All `last` bits for lanes 0 to N−2 inclusive must be driven low by the source, and may be ignored by the sink.](https://abs-tudelft.github.io/tydi/specification/physical.html#last-signal-description)
C < 8: [All `strb` bits must be driven to the same value by the source. The sink only needs to interpret one of the bits.](https://abs-tudelft.github.io/tydi/specification/physical.html#strb-signal-description) (`strb` effectively doesn't exist, except to indicate empty sequences)
C < 6: [`stai` must always be driven to 0 by the source, and may be ignored by the sink.](https://abs-tudelft.github.io/tydi/specification/physical.html#stai-signal-description) (Elements are aligned to lane 0.)
C < 5: [`endi` must be driven to N−1 by the source when `last` is zero, and may be ignored by the sink in this case.](https://abs-tudelft.github.io/tydi/specification/physical.html#endi-signal-description) (Effectively, all lanes must be used, except when transferring the end of a sequence.)
C < 4: [It is illegal to assert the `last` bit for dimension 0 when the respective data lane is inactive, except for empty sequences.](https://abs-tudelft.github.io/tydi/specification/physical.html#last-signal-description) (Effectively, `last` may not be postponed.)

## Issue

Taking a sequence of 7 elements with dimensionality D = 1 over a physical stream with 4 element lanes and complexity C < 4:

Transfer 1:
`[active, active, active, active`
All lanes must be used, because stai must be 0, and endi must be N-1. (Because C < 5 and C < 6)

Transfer 2:
`active, active, active], inactive` ?
The `data` must be aligned to lane 0 (C < 6: stai must be 0)
The `last` of dimension 0 must be asserted on the third lane. (C < 4: It is illegal to assert the last bit for dimension 0 when the `data` of that lane is inactive.)
But also, the last of any dimension must actually be asserted on the fourth lane? (C < 8: last of lanes 0 through N-2 must be driven low. strb effectively doesn’t exist.)

## Assumed/Suggested Fix

The key inconsistency is derived from:

> C < 4 It is illegal to assert the `last` bit for dimension 0 when the **respective data lane** is inactive, except for empty sequences.

At C < 8, the `last` signal does not refer to specific data lanes, but operates on a per-transfer level. The intent of this rule is to prevent postponing the `last` signal, not to establish requirements for data lanes with respect to the `last` signal. Hence, the rule should probably be changed to say:

> C < 4 It is illegal to assert the `last` bit for dimension 0 when the **transfer data** is inactive, except for empty sequences.

or

> C < 4 It is illegal to assert any last bit when the **transfer** data is inactive, except for empty sequences.

Review the Tydi physical specification sections on signals, focusing on 'last', 'strb', 'stai', and 'endi' for complexities C < 4, C < 5, C < 6, and C < 8. Examine the example with 7 elements, 4 lanes, and D=1 to understand the conflict. The fix involves clarifying the rule about asserting 'last' when data is inactive, likely in the specification document itself.

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