Owner

OpenXiangShan

16 indexed repositories · View on GitHub

• XiangShan

  Open-source high-performance RISC-V processor

  Scala · 7268 stars

• XiangShan-doc

  Documentation for XiangShan

  Markdown · 445 stars

• NEMU

  Super fast RISC-V ISA emulator for XiangShan processor

  C · 349 stars

• difftest

  Modern co-simulation framework for RISC-V CPUs

  C++ · 184 stars

• GEM5

  C++ · 159 stars

• YuQuan

  Scala · 101 stars

• gsim

  C++ · 82 stars

• XiangShan-Design-Doc

  Documentation for XiangShan Design

  Markdown · 51 stars

• nexus-am

  C · 45 stars

• XiangShanLab

  A learning and practice repository for the open-source XiangShan RISC-V processor, featuring a full pathway from environment setup to mic...

  Scala · 38 stars

• YunSuan

  This repo includes XiangShan's function units

  Scala · 33 stars

• Deterload

  Xiangshan deterministic workloads generator

  Nix · 28 stars

• ChiselAIA

  RISC-V AIA in Chisel

  Scala · 13 stars

• ready-to-run

  Shell · 11 stars

• LibCheckpoint

  C · 4 stars

• ChiselIOPMP

  An open-sourced Chisel implementation of the RISC-V I/O Physical Memory Protection (IOPMP).

  Scala · 3 stars