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OpenXiangShan

16 indexed repositories · View on GitHub

XiangShan
Open-source high-performance RISC-V processor

Scala · 7268 stars
XiangShan-doc
Documentation for XiangShan

Markdown · 445 stars
NEMU
Super fast RISC-V ISA emulator for XiangShan processor

C · 349 stars
difftest
Modern co-simulation framework for RISC-V CPUs

C++ · 184 stars
GEM5

C++ · 159 stars
YuQuan

Scala · 101 stars
gsim

C++ · 82 stars
XiangShan-Design-Doc
Documentation for XiangShan Design

Markdown · 51 stars
nexus-am

C · 45 stars
XiangShanLab
A learning and practice repository for the open-source XiangShan RISC-V processor, featuring a full pathway from environment setup to mic...

Scala · 38 stars
YunSuan
This repo includes XiangShan's function units

Scala · 33 stars
Deterload
Xiangshan deterministic workloads generator

Nix · 28 stars
ChiselAIA
RISC-V AIA in Chisel

Scala · 13 stars
ready-to-run

Shell · 11 stars
LibCheckpoint

C · 4 stars
ChiselIOPMP
An open-sourced Chisel implementation of the RISC-V I/O Physical Memory Protection (IOPMP).

Scala · 3 stars

Beginner friendly Everything

Open All

[aw] Repo Status hit engine rate limit (HTTP 429) Open

agentic-workflows

Difficulty 4/5 3-5 days Newbie friendliness 35/100

OpenXiangShan/GEM5#1177 · Opened Sep 20, 2026
Spurious page fault on first access to Sv39 4 KiB leaf mappings without any prior sfence.vma — kunminghu-v2 Open

module: unknown type: bug/reported

Difficulty 5/5 Over a week Newbie friendliness 32/100

OpenXiangShan/XiangShan#6606 · Opened Sep 20, 2026
[Project] <Continuous Development of RISC-V Verification Tooling for the XiangShan Processor> Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

OpenXiangShan/XiangShanLab#90 · Opened Sep 20, 2026
M-mode strided and indexed vector accesses are not stopped by a locked PMP entry Open

module: unknown type: bug/reported

Difficulty 4/5 3-5 days Newbie friendliness 48/100

OpenXiangShan/XiangShan#6605 · Opened Sep 20, 2026
vl=0 unit-stride vector loads (vle8/16/32/64.v, masked and unmasked) wrongly set mstatus.VS to Dirty on kunminghu-v2 — residual load path of #6561 Open

module: unknown type: bug/reported version: kunminghu-v2

Difficulty 4/5 3-5 days Newbie friendliness 50/100

OpenXiangShan/XiangShan#6602 · Opened Sep 20, 2026
[Project] <Memory Safety Test for Xiangshan> Open

OpenXiangShan/XiangShanLab#89 · 1 comment · 1 assignee · Opened Sep 20, 2026
[TASK] AI 基础算法 Open

OpenXiangShan/XiangShanLab#88 · 4 comments · 1 assignee · Opened Sep 20, 2026
[TASK] scalar-mul-div 指令生命周期分析 Open

OpenXiangShan/XiangShanLab#87 · 6 comments · 1 assignee · Opened Sep 20, 2026
[aw] Repo Status hit engine rate limit (HTTP 429) Open

agentic-workflows

Difficulty 4/5 3-5 days Newbie friendliness 38/100

OpenXiangShan/GEM5#1176 · Opened Sep 19, 2026
[BUG] DUT vector register writes never reach the REF state (vregs stuck at initial pattern) Open

Difficulty 4/5 3-5 days Newbie friendliness 52/100

OpenXiangShan/difftest#969 · Opened Sep 19, 2026
vsm.v store access fault reports the base address in mtval instead of the first faulting byte Open

module: memory type: bug/WIP feature version: kunminghu-v3

Difficulty 4/5 3-5 days Newbie friendliness 52/100

OpenXiangShan/XiangShan#6599 · 1 comment · Opened Sep 19, 2026
Several vector instruction families permanently stall the core (no trap, no commit) Open

module: unknown type: bug/WIP feature version: kunminghu-v3

Difficulty 4/5 3-5 days Newbie friendliness 48/100

OpenXiangShan/XiangShan#6598 · 1 comment · Opened Sep 19, 2026
VirtualStoreQueue `retirePtr update error!` assertion and a commit stall after a multi-register segmented vector store followed by an AMO (regression between ede751b7c and c8d7b3a5c) — kunminghu-v3 Open

module: unknown type: bug/WIP feature version: kunminghu-v3

Difficulty 4/5 3-5 days Newbie friendliness 48/100

OpenXiangShan/XiangShan#6597 · 1 comment · Opened Sep 19, 2026
A **faulting** segment load with `nf >= 3` trips `robEntries ... uopNum is overflow!` Open

module: unknown type: bug/reported version: kunminghu-v2

OpenXiangShan/XiangShan#6596 · 1 comment · 1 assignee · Opened Sep 18, 2026
M-mode `cbo.*` to a block denied by a **locked** PMP entry is not trapped Open

module: memory type: bug/reported

OpenXiangShan/XiangShan#6595 · 1 comment · 1 assignee · Opened Sep 18, 2026
`vsetivli` with AVL = 0 sets `vtype.vill` when it follows an LMUL = 8 configuration Open

module: unknown type: bug/WIP feature version: kunminghu-v3

Difficulty 4/5 3-5 days Newbie friendliness 68/100

OpenXiangShan/XiangShan#6594 · 1 comment · Opened Sep 18, 2026
[aw] Repo Status hit engine rate limit (HTTP 429) Open

agentic-workflows

Difficulty 4/5 3-5 days Newbie friendliness 28/100

OpenXiangShan/GEM5#1174 · Opened Sep 17, 2026
[TASK] 跨物理页取指异常 bug #5910 #5872 Open

OpenXiangShan/XiangShanLab#85 · 1 comment · 1 assignee · Opened Sep 17, 2026
[TASK] FENCE.TIME 指令实现 Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

OpenXiangShan/XiangShanLab#84 · 1 comment · Opened Sep 17, 2026
[TASK] 嵌套异常 bug #6303 Open

Difficulty 3/5 1-2 days Newbie friendliness 52/100

OpenXiangShan/XiangShanLab#83 · 6 comments · Opened Sep 17, 2026
[TASK] XiangShan AMO Bug #6343 #6294 #6289 Open

Difficulty 4/5 3-5 days Newbie friendliness 55/100

OpenXiangShan/XiangShanLab#82 · 1 comment · Opened Sep 17, 2026
[aw] Repo Status hit engine rate limit (HTTP 429) Open

agentic-workflows

Difficulty 4/5 3-5 days Newbie friendliness 35/100

OpenXiangShan/GEM5#1169 · Opened Sep 16, 2026
`mtval` is not written on a load access fault taken by a vector strided load (`vlse32.v`) — kunminghu-v3 Open

module: memory type: bug/WIP feature version: kunminghu-v3

Difficulty 4/5 3-5 days Newbie friendliness 50/100

OpenXiangShan/XiangShan#6576 · 1 comment · Opened Sep 16, 2026
Missing Instruction Access Fault after `csrw pmpcfg0` Open

module: unknown type: bug/reported

Difficulty 4/5 3-5 days Newbie friendliness 68/100

OpenXiangShan/XiangShan#6575 · 1 comment · Opened Sep 15, 2026
[aw] Repo Status timed out Open

agentic-workflows

Difficulty 3/5 1-2 days Newbie friendliness 58/100

OpenXiangShan/GEM5#1151 · Opened Sep 14, 2026
[aw] Repo Status timed out Open

agentic-workflows

Difficulty 3/5 1-2 days Newbie friendliness 62/100

OpenXiangShan/GEM5#1147 · Opened Sep 13, 2026
[aw] Repo Status hit engine rate limit (HTTP 429) Open

agentic-workflows

Difficulty 4/5 3-5 days Newbie friendliness 45/100

OpenXiangShan/GEM5#1146 · Opened Sep 12, 2026
[aw] Detection Runs Open

agentic-workflows

Difficulty 1/5 Under an hour Newbie friendliness 10/100

OpenXiangShan/GEM5#1145 · 7 comments · Opened Sep 12, 2026
[repo-status] Daily Repo Status: 2026-09-11 - CHIron CCHI fabric opens; custom checkpoint profiles land; SMT LSQ hang fix ready [Content trun Open

daily-status report

Difficulty 1/5 Under an hour Newbie friendliness 15/100

OpenXiangShan/GEM5#1144 · Opened Sep 11, 2026
`vssubu.vx` (vector fixed-point unsigned saturating subtract) does not set `vxsat` when it saturates — kunminghu-v3 Open

module: backend type: bug/WIP feature version: kunminghu-v3

Difficulty 4/5 3-5 days Newbie friendliness 52/100

OpenXiangShan/XiangShan#6555 · 1 comment · Opened Sep 11, 2026
`vsrl.vv` with `v0.t` mask hangs and never writes back the destination register Open

module: backend type: bug/WIP feature version: kunminghu-v3

Difficulty 4/5 3-5 days Newbie friendliness 42/100

OpenXiangShan/XiangShan#6545 · 1 comment · Opened Sep 10, 2026
`vcpop.m` is incorrectly reported as an illegal instruction when `LMUL=8` and `vs2` is not group-aligned Open

module: backend type: bug/WIP feature version: kunminghu-v3

Difficulty 3/5 1-2 days Newbie friendliness 74/100

OpenXiangShan/XiangShan#6544 · 1 comment · Opened Sep 10, 2026
`vdiv.vx` with a zero divisor deadlocks the core Open

module: backend type: bug/WIP feature version: kunminghu-v3

Difficulty 4/5 3-5 days Newbie friendliness 48/100

OpenXiangShan/XiangShan#6543 · 1 comment · Opened Sep 10, 2026
[TASK] XiangShan issue #3844 复现与分析 Open

OpenXiangShan/XiangShanLab#78 · 6 comments · 1 assignee · Opened Sep 10, 2026
[BUG] Sdtrig: tdata1 accepts action=1 (enter Debug Mode) with dmode=0 and without Sdext; a hit then panics NEMU Open

Difficulty 3/5 1-2 days Newbie friendliness 76/100

OpenXiangShan/NEMU#1206 · Opened Sep 10, 2026
Sdtrig: tinfo.version reads 0 although mcontrol6 is implemented with the ratified 1.0 layout Open

Difficulty 2/5 1-3 hours Newbie friendliness 82/100

OpenXiangShan/NEMU#1205 · Opened Sep 10, 2026
HLVX: the PMP/PMA stage checks only read permission; execute permission is not required at the physical level Open

Difficulty 3/5 1-2 days Newbie friendliness 76/100

OpenXiangShan/NEMU#1204 · Opened Sep 10, 2026
BUG] Smrnmi/Smdbltrp: with mnstatus.NMIE=0, a trap taken from S/U-mode becomes a critical error instead of being delivered Open

Difficulty 2/5 1-3 hours Newbie friendliness 78/100

OpenXiangShan/NEMU#1203 · Opened Sep 10, 2026
Sdtrig: address triggers compare (and report) the unmasked virtual address when pointer masking is active Open

Difficulty 4/5 3-5 days Newbie friendliness 65/100

OpenXiangShan/NEMU#1202 · Opened Sep 10, 2026
`vmadc.vi` zeroes mask-destination tail bits Open

module: backend type: bug/WIP feature version: kunminghu-v3

Difficulty 4/5 3-5 days Newbie friendliness 48/100

OpenXiangShan/XiangShan#6536 · 1 comment · Opened Sep 9, 2026
[TASK] RISC-V 异常触发程序批量生成 Open

OpenXiangShan/XiangShanLab#75 · 1 comment · 2 assignees · Opened Sep 9, 2026
[TASK] chisel programming & 2x2 NoC Ring Open

OpenXiangShan/XiangShanLab#74 · 1 comment · 1 assignee · Opened Sep 9, 2026
[TASK] FENCE.TIME 指令实现 Open

enhancement

OpenXiangShan/XiangShanLab#71 · 4 comments · 1 assignee · Opened Sep 9, 2026
[TASK]hello xiangshan & 香山指令 latency throughput 分析 Open

OpenXiangShan/XiangShanLab#68 · 1 comment · 2 assignees · Opened Sep 9, 2026
[作业提交]：hello xiangshan Open

Difficulty 1/5 Under an hour Newbie friendliness 15/100

OpenXiangShan/XiangShanLab#63 · Opened Sep 8, 2026
[Matrix][DiffTest] NEMU AMU control event reports mxrm for floating MMA Open

Difficulty 3/5 1-2 days Newbie friendliness 78/100

OpenXiangShan/NEMU#1201 · Opened Sep 7, 2026
[作业提交]：hello xiangshan Open

Difficulty 1/5 Under an hour Newbie friendliness 15/100

OpenXiangShan/XiangShanLab#57 · 1 comment · Opened Sep 7, 2026
[TASK] 香山代码的docker环境的构建 Open

OpenXiangShan/XiangShanLab#54 · 4 comments · 3 assignees · Opened Sep 7, 2026
[TASK] 完成xiangshan环境的搭建 Open

OpenXiangShan/XiangShanLab#53 · 15 comments · 1 assignee · Opened Sep 7, 2026
[TASK] 学习过程中的课程文档 Open

OpenXiangShan/XiangShanLab#52 · 3 comments · 1 assignee · Opened Sep 7, 2026

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