ucb-bar/testchipip

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Stars: 91
Forks: 91
Open beginner issues: 0
Indexed issues: 18

Dominant language: Scala
License: BSD-3-Clause
Last GitHub push: Aug 14, 2026
Latest indexed: Sep 19, 2026
Contributing guide: No contributing guide
Code of conduct: No code of conduct
Beginner labels: help wanted
PR merge metrics: No merged PRs in 30d

Beginner friendly Everything

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18 open issues indexed

Incorrect CSR State Override Logic Causes Spike State Rollback on RMW Instructions Open

Difficulty 4/5 3-5 days Newbie friendliness 55/100

ucb-bar/testchipip#268 · Opened Jan 9, 2026
bootrom string doesn't allow to set file Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

ucb-bar/testchipip#261 · Opened Oct 15, 2025
Mismatch in CoSpike co-simulation about WLRL CSR registers Open

Difficulty 4/5 3-5 days Newbie friendliness 20/100

ucb-bar/testchipip#258 · Opened Apr 30, 2025
Remove dependency on sifive-blocks Open

Difficulty 4/5 3-5 days Newbie friendliness 30/100

ucb-bar/testchipip#156 · 1 comment · Opened Jan 18, 2023
It cannot compatible 128 bit data length Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

ucb-bar/testchipip#147 · 2 comments · Opened Jul 11, 2022
Make BlockDevice base address come from Config Open

Difficulty 3/5 1-2 days Newbie friendliness 45/100

ucb-bar/testchipip#131 · 1 comment · Opened Apr 16, 2021
Make SimDRAM work when physical address width > 32 bits. Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 35/100

ucb-bar/testchipip#127 · Opened Mar 29, 2021
TSI Host Widget Full Integration Test Open

enhancement help wanted

Difficulty 4/5 3-5 days Newbie friendliness 25/100

ucb-bar/testchipip#117 · Opened Jan 8, 2021
TSI Host Widget Documentation Open

enhancement help wanted

Difficulty 3/5 1-2 days Newbie friendliness 45/100

ucb-bar/testchipip#116 · Opened Jan 8, 2021
value += is not a member of String Open

Difficulty 3/5 1-2 days Newbie friendliness 35/100

ucb-bar/testchipip#95 · Opened Jul 23, 2020
SerialAdapter should require minLatency > 0 Open

Difficulty 4/5 3-5 days Newbie friendliness 42/100

ucb-bar/testchipip#88 · 2 comments · Opened Jun 13, 2020
Use PlusArgArtefacts.append to avoid emulator.cc hacks in next RC bump Open

Difficulty 3/5 1-2 days Newbie friendliness 35/100

ucb-bar/testchipip#86 · Opened May 21, 2020
Eventually move to the `InModuleBody` paradigm instead of `ModuleImp`s to mirror rocket-chip Open

Difficulty 5/5 Over a week Newbie friendliness 15/100

ucb-bar/testchipip#77 · Opened Apr 16, 2020
Import issue: compile fails, can't find UARTPortIO Open

Difficulty 3/5 1-2 days Newbie friendliness 35/100

ucb-bar/testchipip#72 · Opened Mar 24, 2020
Provide parameterization of SERIAL_IF_WIDTH Open

Difficulty 2/5 1-3 hours Newbie friendliness 50/100

ucb-bar/testchipip#63 · 1 reaction · Opened Jan 18, 2020
Bidirectional serdes safe usage Open

Difficulty 4/5 3-5 days Newbie friendliness 30/100

ucb-bar/testchipip#49 · 2 comments · Opened Jul 12, 2019
ClockUtil unit tests Open

Difficulty 3/5 1-2 days Newbie friendliness 35/100

ucb-bar/testchipip#40 · 1 reaction · Opened Mar 28, 2019
Making Host/Target coordination for the TLSerdesser easier Open

enhancement

ucb-bar/testchipip#37 · 2 comments · 1 assignee · Opened Mar 5, 2019

ucb-bar/testchipip

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