lnls-dig/bpm-gw

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Repository containing the gateware for the Beam Position Monitor project

Stars: 12
Forks: 2
Open beginner issues: 0
Indexed issues: 14

Dominant language: C
License: LGPL-3.0
Last GitHub push: Sep 27, 2024
Latest indexed: Sep 19, 2026
Contributing guide: No contributing guide
Code of conduct: No code of conduct
Beginner labels: No beginner labels indexed
PR merge metrics: No merged PRs in 30d

Beginner friendly Everything

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14 open issues indexed

Incorrect comments in the FMC ADCs SPI interface Open

Difficulty 1/5 Under an hour Newbie friendliness 35/100

lnls-dig/bpm-gw#110 · Opened Oct 24, 2024
[MONIT1/MONIT tag delay] delays are applied as "ADC clock cycles" granularity Open

bug

lnls-dig/bpm-gw#81 · 1 assignee · Opened Jul 8, 2020
[FOFB sync] FOFB sync only works when switching is in "switching" mode Open

bug

lnls-dig/bpm-gw#80 · 1 assignee · Opened Jul 8, 2020
[wb_fmcpico1m_4ch] Aquisition clock must be synchonized with machine clock Open

bug

lnls-dig/bpm-gw#79 · 1 assignee · Opened Jun 26, 2020
Allow simulataneous range selection on XBPM gateware Open

enhancement

lnls-dig/bpm-gw#78 · 1 assignee · Opened Jun 10, 2020
[wb_trigger] Add enable input in each logical trigger Open

enhancement

Difficulty 5/5 Over a week Newbie friendliness 35/100

lnls-dig/bpm-gw#74 · Opened Aug 18, 2018
[acq_core] More options for data-driven trigger Open

enhancement

Difficulty 4/5 3-5 days Newbie friendliness 35/100

lnls-dig/bpm-gw#71 · Opened Jul 13, 2017
[wb_trigger_iface] Missing pulse extender check if length = 0 Open

bug

Difficulty 2/5 1-3 hours Newbie friendliness 45/100

lnls-dig/bpm-gw#69 · Opened Jun 23, 2017
[flash_loader] Implement Flash Loader via PCIe/Wishbone Open

enhancement

Difficulty 5/5 Over a week Newbie friendliness 25/100

lnls-dig/bpm-gw#55 · Opened Apr 27, 2016
[fmc130m] Top .ucf .xdc files for FMC130M are misleading Open

Difficulty 2/5 1-3 hours Newbie friendliness 50/100

lnls-dig/bpm-gw#53 · Opened Feb 19, 2016
[vivado_project] AXI Interconnect BPM is not generated as VHDL and simulation fails Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 30/100

lnls-dig/bpm-gw#51 · Opened Dec 18, 2015
[pcie_core] Cannot access DDR data from high address Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 35/100

lnls-dig/bpm-gw#45 · 2 comments · Opened Jun 12, 2015
[wb_acq_core] Check lmt_curr_chan_id signal and its use Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 35/100

lnls-dig/bpm-gw#43 · Opened Mar 25, 2015
[wb_fmc130m_4ch] ADC clock current delay value not used Open

Difficulty 4/5 3-5 days Newbie friendliness 38/100

lnls-dig/bpm-gw#39 · Opened Oct 14, 2014

lnls-dig/bpm-gw

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