llvm / llvm/circt

[OM] Shift left folder doesnt sign extend

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FIRRTL OM
Dominant language
C++
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Description

The shift-left folder will do modular shift left, respecting the size of the underlying ap-int, but since we're working with big integers, I'd expect it to grow instead.

Demo of the issue, 4 << 4 ==> 0

firrtl.circuit "Casts" {
  firrtl.module @Casts() {}
  firrtl.class @PropertyArithmetic(out %o1: !firrtl.integer) {
    %0 = firrtl.integer 4
    %1 = firrtl.integer.shl %0, %0 : (!firrtl.integer, !firrtl.integer) -> !firrtl.integer
    firrtl.propassign %o1, %1 : !firrtl.integer
  }
}

// ./bin/circt-opt -canonicalize='top-down=true region-simplify=aggressive' ../scratch/scratch.mlir  --mlir-print-ir-before-all
module {
  firrtl.circuit "Casts" {
    firrtl.module @Casts() {
    }
    firrtl.class @PropertyArithmetic(out %o1: !firrtl.integer) {
      %0 = firrtl.integer 0
      firrtl.propassign %o1, %0 : !firrtl.integer
    }
  }
}

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First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Start by running the provided firrtl.integer.shl MLIR example through circt-opt with the shown canonicalization options and inspect the integer shift folding path. The fix is complete when shifting 4 left by 4 produces 16 rather than 0, with coverage for the corrected behavior.

Written by the indexing model from the issue text.

Assessment

Tech stack
cpp
Domain
compilers
Issue type
Bug
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
45/100

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