[HW] Implement HW Dialect IMDCE

Implement a HW-dialect level inter-module dead code elimination pass.

### Example

I'm specifically motivating this for situations in which the optimizations at the FIRRTL Dialect level are insufficient to fully optimize things. This can frequently come up for situations involving registers and assertions. Consider the following reduced example:

``` mlir
hw.module @Foo(in %clock : !seq.clock, in %reset : i1) {
%false = hw.constant false
%true = hw.constant true
%r = seq.firreg %false clock %clock reset sync %reset, %true {firrtl.random_init_start = 0 : ui64} : i1
hw.output
}
```

This is a trivially unused register which FIRRTL Dialect's IMDCE will happily rip out. However, this will be preserved into the output Verilog (`firtool -disable-all-randomization Foo.fir`):

``` verilog
// Generated by CIRCT firtool-1.138.0-70-g89655abab
module Foo(
input clock,
reset
);

reg r;
always @(posedge clock) begin
if (reset)
r <= 1'h1;
else
r <= 1'h0;
end // always @(posedge)
endmodule
```

Operations which are even more trivially unused, e.g., dead wires, will get removed. However, we really need this for unused loops of non-side-effecting connectivity.

Start by reproducing the Foo.fir example with `firtool -disable-all-randomization` and compare the HW-dialect and FIRRTL-dialect IMDCE behavior. Trace the HW dialect pass entry point and its handling of side-effecting operations; done means unused registers and non-side-effecting connectivity loops are eliminated without removing required behavior.

Written by the indexing model from the issue text.