Add Module Prefix to Generated Verilog

Add support for adding a user-defined prefix to all emitted Verilog modules in the design.

Users of llvm/circt want to integrate the Verilog we produce with a larger, hand-written or third-party Verilog design. However, this can cause name conflicts. E.g., names like "Queue" or "ALU" will frequently conflict. This can be trivially fixed by allowing users to set a prefix that will be prepended to all emitted module names.

E.g., if you compiled the following FIRRTL snippet (Foo.fir):

circuit Foo:
  module Bar: 
    skip

You would normally get (from something like firtool -verilog Foo.fir):

module Foo();
endmodule

However, if you instead did firtool -verilog -prefix=Bar_ Foo.fir, you would get:

module Bar_Foo();
endmodule

For implementation, this can either be a pass (on RTL or Verilog) or Verilog emitter pre-pass that mangles the names. Alternatively, this could be a "namespace" operation added to one of the core dialects that has the effect of being lowered to a name. (This latter is probably more general.)

Start by tracing the firtool -verilog flow and its Verilog emission path. Compare the proposed RTL/Verilog name-mangling pass with adding a namespace operation, then define how the user-supplied prefix applies to every emitted module. Done means a prefix such as Bar_ produces consistently prefixed Verilog module names without conflicts.