circt-verilog --ir-hw produces multiple seq.firreg for a single Verilog reg

Nobody has claimed this yet.

multiple drivers maybe should error

```
module test (
input clk,
input rst_n,
input b,
output wire x
);
reg a;
always @(posedge clk or negedge rst_n)
if (!rst_n)
a <= 0;
else if (b)
a <= 1;

always @(posedge clk or negedge rst_n)
if (!rst_n)
a <= 0;
else if (b)
a <= 0;

assign x = a;
endmodule
```
after circt-veirlog --ir-hw
```
module {
hw.module @fifo(in %clk : i1, in %rst_n : i1, in %b : i1, out x : i1) {
%true = hw.constant true
%false = hw.constant false
%0 = seq.to_clock %clk
%1 = comb.xor %rst_n, %true : i1
%2 = comb.mux bin %b, %b, %a : i1
%a = seq.firreg %2 clock %0 reset async %1, %false : i1
%3 = comb.xor %b, %true : i1
%4 = comb.and %3, %a_0 : i1
%a_0 = seq.firreg %4 clock %0 reset async %1, %false {name = "a"} : i1
hw.output %a_0 : i1
}
}
```

Reproduce the Verilog example with circt-verilog --ir-hw and compare the generated IR, focusing on the two seq.firreg operations for a. Clarify whether multiple drivers should produce an error or a different lowering, then add coverage for the chosen behavior and verify the generated IR or diagnostic.

Written by the indexing model from the issue text.