ExportVerilog: Do not print ifdefs when there is nothing to print

The following FIRRTL code creates a verilog module with an empty ifdef block. The reason is that, although there are canonicalizers in place which will clean up empty ifdefs, when the ifdef contains only a "do not print" instance, it will still be printed, even though the instance will not.

``` firrtl
FIRRTL version 5.0.0

circuit Foo:
layer A, inline:
layer B, bind:

public module Foo:
input clock : Clock
input cond : UInt<1>
input enable : UInt<1>

layerblock A:
layerblock B:
assert(clock, cond, enable, "message")
```

``` verilog
// Generated by CIRCT 765883a39
module Foo_A_B(); // within split at ../test/firtool/layers.fir:67 offset :32:7
always @(posedge Foo.clock) begin // within split at ../test/firtool/layers.fir:67 offset :27:11, :33:9
if (Foo.enable) // within split at ../test/firtool/layers.fir:67 offset :29:11, :33:9
assert(Foo.cond) else $error("message"); // within split at ../test/firtool/layers.fir:67 offset :28:11, :33:9
end // always @(posedge)
endmodule

module Foo( // within split at ../test/firtool/layers.fir:67 offset :26:10
input clock, // within split at ../test/firtool/layers.fir:67 offset :27:11
cond, // within split at ../test/firtool/layers.fir:67 offset :28:11
enable // within split at ../test/firtool/layers.fir:67 offset :29:11
);

`ifdef layer$A // within split at ../test/firtool/layers.fir:67 offset :31:5
`endif // layer$A
endmodule

// ----- 8< ----- FILE "layers-Foo-A-B.sv" ----- 8< -----

// Generated by CIRCT 765883a39
`ifndef layers_Foo_A_B // within split at ../test/firtool/layers.fir:67 offset :26:10
`define layers_Foo_A_B
`ifndef layer$A // within split at ../test/firtool/layers.fir:67 offset :26:10
`_ERROR_A_not_enabled
`endif // not def layer$A
bind Foo Foo_A_B a_b ();
`endif // not def layers_Foo_A_B
```