FIRParser: Errors during parsing only point at the .fir file

Nobody has claimed this yet.

We have been trying to move FIRRTL towards using "constructively correct" operations, and moving user facing errors away from using op verifiers, which mean that we are emitting more errors from the FIRRTL parser. While this seems generally good, as we have less things to check and won't be dumping internal IR state, I have noticed that these errors must point to a location in the `.fir` file, and can't point to a location in the Scala file.

For example:
```scala
//> using scala "2.13.12"
//> using dep "org.chipsalliance::chisel:6.7.0"
//> using plugin "org.chipsalliance:::chisel-plugin:6.7.0"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage
import chisel3.probe._

class MyBundle() extends Bundle {
val a = Flipped(Bool())
}
class Foo extends Module {
val a = IO(new MyBundle)
val wire = Wire(new MyBundle())
forceInitial(RWProbeValue(wire), a)
}

object Main extends App {
println(
ChiselStage.emitSystemVerilog(
gen = new Foo,
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
)
)
}
```

running `scala-cli chisel-example.scala`, gives:
```
Compiling project (Scala 2.13.12, JVM (17))
Compiled project (Scala 2.13.12, JVM (17))
Exception in thread "main" circt.stage.phases.Exceptions$FirtoolNonZeroExitCode: /sifive/tools/llvm/circt/1.125.0/bin/firtool returned a non-zero exit code. Note that this version of Chisel (6.7.0) was published against firtool version 1.62.1.
------------------------------------------------------------------------------
ExitCode:
1
STDOUT:

STDERR:
:9:5: error: expected passive value for force_initial source, got '!firrtl.bundle>'
force_initial(rwprobe(wire), a) @[chisel-example.scala 17:15]
^
```

It would be nicer if this error message was able to point directly to the input Scala file. I notice that as more checking is being done in Chisel itself, this kind of issue becomes harder to see.

The issue concerns FIRRTL parser diagnostics invoked through firtool and ChiselStage; start by tracing how the parser receives and emits source locations for the shown force_initial error. Done means the diagnostic can point to the originating Scala file instead of only the .fir input location, with the example serving as the validation case.

Written by the indexing model from the issue text.