[Mem2Reg] Local signal does not dominate final drive

For input (derived from SV import minized and then MLIR minized)

```mlir
module {
hw.module @a() {
%false = hw.constant false
%b = llhd.sig %false : i1
llhd.combinational {
cf.br ^bb2
^bb1: // no predecessors
%0 = llhd.prb %b : !hw.inout
%1 = llhd.constant_time <0ns, 0d, 1e>
%g = llhd.sig %false : i1
llhd.drv %g, %0 after %1 : !hw.inout
cf.br ^bb2
^bb2: // 2 preds: ^bb0, ^bb1
llhd.yield
}
hw.output
}
}
```

results post llhd-mem2reg in

```
error: operand #0 does not dominate this use
note: see current operation: "llhd.drv"(%6, %7, %9, %8) : (!hw.inout, i1, !llhd.time, i1) -> ()
/tmp/t2.mlir:10:12: note: operand defined here (op in the same region)
%g = llhd.sig %false : i1
^
```

print IR after:

```mlir
"builtin.module"() ({
"hw.module"() <{module_type = !hw.modty<>, parameters = [], sym_name = "a"}> ({
%0 = "hw.constant"() <{value = false}> : () -> i1
%1 = "llhd.sig"(%0) <{name = "b"}> : (i1) -> !hw.inout
%2 = "llhd.prb"(%1) : (!hw.inout) -> i1
"llhd.combinational"() ({
%3 = "hw.constant"() <{value = false}> : () -> i1
%4 = "hw.constant"() <{value = false}> : () -> i1
"cf.br"(%3, %4)[^bb2] : (i1, i1) -> ()
^bb1: // no predecessors
%5 = "hw.constant"() <{value = true}> : () -> i1
%6 = "llhd.sig"(%0) <{name = "g"}> : (i1) -> !hw.inout
"cf.br"(%2, %5)[^bb2] : (i1, i1) -> ()
^bb2(%7: i1, %8: i1): // 2 preds: ^bb0, ^bb1
%9 = "llhd.constant_time"() <{value = #llhd.time<0ns, 0d, 1e>}> : () -> !llhd.time
"llhd.drv"(%6, %7, %9, %8) : (!hw.inout, i1, !llhd.time, i1) -> ()
// ^
"llhd.yield"() : () -> ()
}) : () -> ()
"hw.output"() : () -> ()
}) : () -> ()
}) : () -> ()
```

Start by reproducing the failure with the provided /tmp/t2.mlir input and the llhd-mem2reg pass after the SV and MLIR minization steps. Inspect the pass output around the llhd.combinational block and its final llhd.drv; done means the transformed IR verifies without a dominance error and the local signal correctly dominates the drive.

Written by the indexing model from the issue text.