Support for Adding Parameter Annotations to Generated Modules (e.g., as Comments)

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### Context
I'm using PyCDE to generate parameterized modules and test them using a handwritten Verilator testbench. To simplify the testbench logic, I instantiate different versions of the module under test using a single testbench. For that to work, all the modules must have the same top-level name.

To achieve this, I prefixed the module builder's argument with an underscore ("_"). With that, generated module's name doesn't contain parameters and is unified, but it creates another problem…
### Problem
By removing the parameters from the module name, I lose visibility into what configuration a given module was generated from. This makes it difficult to track which parameters were used for which module, especially when dealing with multiple variations. As a result, debugging and traceability suffer.
### Question/Feature Request
Is there a way to annotate the generated Verilog/SystemVerilog module with a comment that includes the parameter values? Ideally, I’d like to see something like this:
```verilog
// Parameters: WIDTH=32, DEPTH=64
module my_module (...);
```
If this is already supported in PyCDE, could you provide an example of how to do it? If not, would it be feasible to add such a feature?

The issue names PyCDE generation and generated Verilog/SystemVerilog output but no files, tests, or entry points. Start by tracing the PyCDE module-generation path and checking whether parameter values are retained for emission; done means generated modules visibly include the requested parameter values in comments.

Written by the indexing model from the issue text.