[ImportVerilog] Request to expose a SystemVerilog Top in FIRRTL

We are trying to link SystemVerilog against FIRRTL at CIRCT time.
I'm requesting a API to expose SystemVerilog as FIRRTL Blackbox, being able to inspect via C-API, which can be linked to other modules later in the FIRRTL.
This feature originally is done in [AutoBlackBox](https://github.com/chipsalliance/chisel/blob/6603b9860ce9eddd0520ad1978137b248fdef01a/src/main/scala/chisel3/util/experimental/AutoBlackBox.scala#L10) in Chisel, however to do it more elegantly, it's necessary to migrate this feature to CIRCT.

Start by reading Chisel's src/main/scala/chisel3/util/experimental/AutoBlackBox.scala at the linked location, then trace how FIRRTL and CIRCT represent black boxes and how their C-API exposes modules. Clarify the intended API for exposing a SystemVerilog top and linking it with later FIRRTL modules; completion criteria are not specified in the issue.

Written by the indexing model from the issue text.