[ImportVerilog] Support Delay control

The [chipsalliance tests for delay control](https://chipsalliance.github.io/sv-tests-results/?v=circt_verilog+9.4.1+always) currently fail. For instance:
```systemverilog
module always_tb ();
logic a = 0;
always #5 a = ~a;
endmodule
```

It should be possible to support SystemVerilog delay controls by lowering `slang::ast::DelayControl` to `llhd::WaitOp` right?

Edit: Realised that it would have to go through Moore dialect first. Not sure what to use there; is it currently doable in Moore?

Start by reproducing the chipsalliance delay-control failures, including the shown always-block example, and inspect the ImportVerilog path for slang::ast::DelayControl. Determine how the Moore dialect should represent the control before lowering it to llhd::WaitOp. Done means the relevant chipsalliance tests pass.

Written by the indexing model from the issue text.