[circt-verilog][llhd][arcilator] Verilog-to-LLVM lowering issues

Hi all!

There are a few issues related to moore to llvm lowering pipeline.

Currently there is no possibility to lower combination logic with control flow operators into LLVM. For example:

```verilog
module top (
input clk ,
input rstn ,
input in
output out
);

parameter P1 = 3'd0 ;
parameter P2 = 3'd3 ;

reg [2:0] r1 = 3'd1;

always_comb begin
if (in)
r1 = P1;
else
r1 = P2;
end
endmodule
```

because it fails with this : `error: failed to legalize operation 'llhd.constant_time'`

And also `arcilator` fails to lower sequential logic which contains both blocking and nonblocking assignments like this example:

```verilog
module top (
input clk ,
input rstn ,
input in
output out
);

parameter P1 = 3'd0 ;
parameter P2 = 3'd3 ;

reg [2:0] r1 = 3'd1;

always @(posedge clk or negedge rstn) begin
r1 = P1;
r1 <= P2 + r1;
end

endmodule
```

because it fails with that:

```
error: body contains non-pure operation
%2 = comb.add %1, %c3_i3 : i3
```

I'm using to lower a such cmd:

```
circt-verilog sample.sv | arcilator
```

Also I tried to add into "populate LLHD" pipeline a newly added passes -- "llhd-hoist-signals" and "llhd-mem2reg". It didn't help.

Maybe I'm doing something wrong or what could be the issue?

1) What are the plans for improving verilog-to-llvm lowering and do they exist at all?
2) Will the "llhd-hoist-signals" and "llhd-mem2reg" passes be added to the `circt-verilog` tool or will they stay standalone?

@fabianschuiki @maerhart

Reproduce the examples from sample.sv using `circt-verilog sample.sv | arcilator`, then inspect the populate LLHD pipeline and the reported `llhd-hoist-signals` and `llhd-mem2reg` passes. Done means determining why the control-flow and mixed-assignment cases fail and recording whether those passes belong in `circt-verilog`, along with the project's stated improvement plans.

Written by the indexing model from the issue text.