Status and getting started
Nobody has claimed this yet.
- Dominant language
- C++
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Description
Hello,
I just arrived here, looking for what I heard was "the LLVM of FPGA/ASIC".
After heading to the front page, and trying to find some instructions to get started, I had a hard way finding about the status of this. I got to multiple dead links, then found some sparse documentation, or links saying that it was similar to MLIR and directing towards MLIR tutorials.
Since all was so sparse and quite in-digest, I ended up thinking that the project was largely abandoned (the articles stated in the website all date from 2020 or 2021).
However, the activity in this repo led me to realize that no, the project is in fact not dead at all.
So. What can currently be done with this? Is there a way to get a bitstream or equivalent from Verilog/VHDL/other?
How is it/can it be used in its current state? Would it be a working language backend?
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with the repository front page, existing getting-started material, and the MLIR tutorial links mentioned in the issue. Inventory dead or sparse links and verify the project's current capabilities and supported paths from Verilog, VHDL, or other inputs; done means a clear, current status and getting-started guide with working links.
Written by the indexing model from the issue text.
Assessment
- Domain
- documentation
- Issue type
- Documentation
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100