[FIRRTL] IMDCE: not removing all dead instances
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FIRRTL
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- C++
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Description
For the following test, I expect both instances m and p to be removed, but for some reason only p is removed:
circuit Foo:
module Foo:
input in : UInt<1>
output out : UInt<1>
output out2 : UInt<1>
inst m of Child
m.in <= in
inst m2 of Child
m2.in <= in
out <= m2.out
inst p of PassThrough
p.in <= in
inst p2 of PassThrough
p2.in <= in
out2 <= p2.out
module PassThrough :
input in : UInt<1>
output out : UInt<1>
out <= in
module Child :
input in : UInt<1>
output out : UInt<1>
inst output_chain of PassThrough
output_chain.in <= in
out <= output_chain.out
running with firtool imdce.fir gives:
// Generated by CIRCT firtool-1.42.0-60-g3093438b0
module Foo(
input in,
output out,
out2
);
Child m (
.in (in),
.out (/* unused */)
);
Child m2 (
.in (in),
.out (out)
);
PassThrough p2 (
.in (in),
.out (out2)
);
endmodule
module PassThrough(
input in,
output out
);
assign out = in;
endmodule
module Child(
input in,
output out
);
PassThrough output_chain (
.in (in),
.out (out)
);
endmodule
This is a regression which was introduced in https://github.com/llvm/circt/pull/5226.
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by running firtool imdce.fir with the FIRRTL reproducer and inspect the IMDCE behavior associated with the regression from pull request 5226. Done means both unused instances m and p are removed while the used instances remain in the generated Verilog.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100