[LLHD] Improve llhd-desequentialize pass

Nobody has claimed this yet.

Hi! I'm trying to erase `llhd.process` by using `llhd-desequentialize` pass in this code:

```verilog
module Mod(input clk, input rstn, output logic b);
always @(posedge clk or negedge rstn)
begin
if (!rstn)
b <= 0;
else
b <= 1;
end
endmodule
```

But it thinks that there are 3 triggers and it couldn't be optimized. How can I support it? As I know, `seq.compreg` supports only one clock and one reset.

Btw, I found another misprint:

https://github.com/llvm/circt/blob/6b4bea036f0768471fa6a5e678dec03e742caf5c/lib/Dialect/LLHD/Transforms/DesequentializationPass.cpp#L655

We should check `triggers[0].kinds.size() != 1` instead of second condition.

Start in lib/Dialect/LLHD/Transforms/DesequentializationPass.cpp around line 655, then trace how llhd-desequentialize handles the Verilog example's three triggers. Correct the noted condition and make the pass support the clock/reset case; done means the example can be desequentialized without the optimization failure.

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