[Verilog][FIRRTL] Improve `$signed` Elision

For certain operations, the Verilog emission can include extra `$signed` casts. This is a lint warning in some tools and it would be good to avoid this.

Consider:

``` firrtl
FIRRTL version 4.0.0
circuit Foo:
public module Foo:
input a: UInt<1>
output c: SInt<4>

connect c, dshr(SInt<4>(3), a)
```

When compiled to Verilog this produces:

``` verilog
// Generated by CIRCT firtool-1.95.1-52-g94a562c5e
module Foo(
input a,
output [3:0] c
);

assign c = $signed(4'sh3 >>> a);
endmodule
```

The extra `$signed` here should be unnecessary.

Care should be taken to not make mistakes that things incorrectly become unsigned and break simulation.

Start by reproducing the FIRRTL example through firtool and inspecting the Verilog emission path responsible for the generated shift expression. The work is done when the unnecessary $signed cast is absent without changing signedness or simulation behavior; add or run focused coverage for this example if the relevant test location is identified.

Written by the indexing model from the issue text.