[FIRRTL] FIRRTL to RTL Memory Lowering Needs to Handle All Read Under Write Behaviors

Nobody has claimed this yet.

Add support for the "old" read-under-write FIRRTL memory behavior. Currently, this is incorrectly emitted as "new".

The FIRRTL spec defines three read-under-write behaviors for memories. A read-under-write behavior is what happens if you try to read and write the same address on the same cycle These three behaviors are:

1. New (return the value in the memory when the read was made)
2. Old (return the value when the read was requested)
3. Undefined (technically anything, but the Scala FIRRTL Compiler treats this as "compiler's choice" and chooses "New")

Note that this only matters for read latencies > 0. These can be treated as equivalent if the ~read latency == 1~ read latency == 0.

Start by tracing the FIRRTL-to-RTL memory lowering entry point and how read-under-write behaviors are represented. Add coverage for old behavior when read latency is greater than zero, while preserving the existing new and undefined behavior. Done means old returns the value requested before the same-cycle write, rather than being emitted as new.

Written by the indexing model from the issue text.