[FIRRTL] smem with read address from port does not work

Consider the following FIRRTL:

```firrtl
FIRRTL version 4.0.0
circuit Top :
public module Top :
input clock : Clock
input raddr : UInt<6>
input waddr : UInt<6>
input wdata : UInt<8>
output rdata : UInt<8>

smem ram : UInt<8>[64]

write mport w = ram[waddr], clock
connect w, wdata

read mport r = ram[raddr], clock
connect rdata, r
```
Compile this with firtool 1.93.1 and you will get:
```
test.fir:16:5: warning: memory port is never enabled
read mport r = ram[raddr], clock
^
test.fir:16:5: note: see current operation: %r_data, %r_port = chirrtl.memoryport Read %ram {name = "r"} : (!chirrtl.cmemory, 64>) -> (!firrtl.uint<8>, !chirrtl.cmemoryport)
// Generated by CIRCT firtool-1.93.1
module Top(
input clock,
input [5:0] raddr,
waddr,
input [7:0] wdata,
output [7:0] rdata
);

assign rdata = 8'h0;
endmodule
```

If you simply add a node to use as the read address instead of the input port, it works. That is, just change the read port to:
```firrtl
node readAddr = raddr
read mport r = ram[readAddr], clock
connect rdata, r
```
Then the emitted Verilog has a memory instantiated as expected.

Reproduce the FIRRTL example with firtool 1.93.1, then compare it with the variant that assigns raddr to readAddr before the read mport. Trace handling of the direct read-port address and verify that the fixed behavior emits a memory and preserves the read data path in Verilog.

Written by the indexing model from the issue text.