[SMT] How to go from Verilog to smtlib2 like with Yosys?

Hi there!

I was exploring whether it was possible to export some simple design from verilog [to some smtlib2 representation like with Yosys](https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/write_smt2.html).

The following naive experiment produced an empty file.

my_or.v
```
module my_or (
input logic a_i,
input logic b_i,
output logic y_o
);
assign y_o = a_i | b_i;
endmodule
```

The commands I run:
```
circt-verilog my_or.sv -o my_or.mlir
circt-opt --convert-hw-to-smt --convert-comb-to-smt my_or.mlir -o my_or_postop.mlir
circt-translate --export-smtlib my_or_postop.mlir -o my_or.smt2
```

Do you have some indications?
Thanks!
Flavien

Reproduce the example using circt-verilog, circt-opt with --convert-hw-to-smt and --convert-comb-to-smt, and circt-translate with --export-smtlib. Inspect the resulting my_or_postop.mlir and the SMT-LIB export path to determine why my_or.smt2 is empty. Done means the sample Verilog produces a non-empty SMT-LIB2 file.

Written by the indexing model from the issue text.