[circt-verilog] zero parameter at module declaration fails when used

I have a mmu.sv module for RISC-V implementation:
```Verilog
module mmu #(
parameter integer DEVICE_COUNT = 0
) (
...
output logic [31:2] dev_addr[DEVICE_COUNT]
...
```

that is used in top module like:

```Verilog
mmu #(
.DEVICE_COUNT(8)
) mmu (
...
.dev_addr(
'{
rom_addr,
ram_addr[0],
ram_addr[1],
ram_addr[2],
ram_addr[3],
led_addr,
mtime_addr,
mtimecmp_addr
}

...
```

when trying to compile with `circt-verilog mmu.sv` i get this error:

```bash
core/mmu.sv:17:34: error: value must be positive
output logic [31:2] dev_addr[DEVICE_COUNT],
```

is it impossible to compile such module? why so?

Start by reproducing the reported error with the mmu.sv example using circt-verilog, focusing on the parameterized dev_addr array dimension and DEVICE_COUNT=0. Compare the behavior when the module is instantiated with DEVICE_COUNT=8, then determine whether zero-sized dimensions should compile or receive a clearer diagnostic.

Written by the indexing model from the issue text.