[FIRRTL] FSRT: not finding all no-reset registers

```firrtl
FIRRTL version 4.0.0
circuit Foo: %[[
{
"class": "circt.FullResetAnnotation",
"target": "~Foo|Foo>r",
"resetType": "sync"
}
]]
public module Foo:
input c : Clock
input i : UInt<8>
input r : UInt<1>
output o : UInt<8>

wire w : UInt<8>
reg reg : UInt<8>, c with:
reset => (r, w)
connect w, reg
connect reg, i
connect o, reg
```
gives:
```verilog
module Foo(
input c,
input [7:0] i,
input r,
output [7:0] o
);

reg [7:0] reg_0;
always @(posedge c) begin
if (r)
reg_0 <= reg_0;
else
reg_0 <= i;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
automatic logic [31:0] _RANDOM[0:0];
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
reg_0 = _RANDOM[/*Zero width*/ 1'b0][7:0];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign o = reg_0;
endmodule
```
Besides the fact that we are missing a canonicalization, it is pretty clear here that the register does not have a reset, and so the FSRT should have added a reset to it.

Start by running the FIRRTL 4.0.0 reproduction and compare its generated Verilog with the issue's output, then trace the FSRT handling of the FullResetAnnotation and no-reset register. Done means the reproduced register receives the expected reset treatment in generated Verilog, with the reported canonicalization concern considered.

Written by the indexing model from the issue text.