[FIRRTL] FRT: treats different encodings of register resets differently

Both registers have a reset, although the first uses the `regreset` representation, and the latter uses a regular `reg` driven by a mux.

```firrtl
FIRRTL version 4.0.0
circuit Foo: %[[
{
"class": "circt.FullResetAnnotation",
"target": "~Foo|Foo>r1",
"resetType": "sync"
}
]]
public module Foo:
input c : Clock
input i : UInt<8>
input r1 : UInt<1>
input r2 : UInt<1>
output o0 : UInt<8>
output o1 : UInt<8>

reg reg0 : UInt<8>, c with:
reset => (r2, UInt<8>(2))
connect reg0, i
connect o0, reg0

reg reg1 : UInt<8>, c
connect reg1, mux(r2, UInt<8>(3), i)
connect o1, reg1

```
gives:
```verilog
module Foo(
input c,
input [7:0] i,
input r1,
r2,
output [7:0] o0,
o1
);

reg [7:0] reg0;
reg [7:0] reg1;
always @(posedge c) begin
if (r2)
reg0 <= 8'h2;
else
reg0 <= i;
if (r1)
reg1 <= 8'h0;
else
reg1 <= r2 ? 8'h3 : i;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
automatic logic [31:0] _RANDOM[0:0];
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
reg0 = _RANDOM[/*Zero width*/ 1'b0][7:0];
reg1 = _RANDOM[/*Zero width*/ 1'b0][15:8];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign o0 = reg0;
assign o1 = reg1;
endmodule
```
The second register ends up with a needless double-reset added by FRT, when it already had a reset.

No source files or tests are named. Start by locating FRT handling for FullResetAnnotation and compare how regreset and mux-driven registers are analyzed. Reproduce the supplied FIRRTL example and inspect the generated Verilog; done means the mux-driven register does not receive an unnecessary additional reset.

Written by the indexing model from the issue text.