[FIRRTL] SFCCompat: can select different values for a single invalid value

Nobody has claimed this yet.

```firrtl
FIRRTL version 4.0.0
circuit Foo: %[[
]]
public module Foo:
input c : Clock
input i0 : UInt<8>
input i1 : UInt<8>
input r : UInt<1>
output o0 : UInt<8>
output o1 : UInt<8>

wire w : UInt<8>
w is invalid

reg reg0 : UInt<8>, c with:
reset => (r, w)
connect reg0, i0
connect o0, reg0

reg reg1 : UInt<8>, c with:
reset => (r, w)
connect reg1, i1
connect o1, reg1

```
gives:
```verilog
module Foo(
input c,
input [7:0] i0,
i1,
input r,
output [7:0] o0,
o1
);

reg [7:0] reg0;
reg [7:0] reg1;
always @(posedge c) begin
reg0 <= i0;
reg1 <= i1;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
automatic logic [31:0] _RANDOM[0:0];
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
reg0 = _RANDOM[/*Zero width*/ 1'b0][7:0];
reg1 = _RANDOM[/*Zero width*/ 1'b0][15:8];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign o0 = reg0;
assign o1 = reg1;
endmodule
```
The resets for both registers are optimized away by SFCCompat, which implies that it selected `w = reg0` when lowering `reg0` and `w = reg1` when lowering `reg1`. It should select a single value for the invalid value.

Reproduce the FIRRTL 4.0.0 example from the issue and inspect SFCCompat's lowering of invalid values used by both reset expressions. Confirm how the same invalid value is selected for reg0 and reg1, then verify that one consistent value is selected and the generated reset behavior no longer diverges.

Written by the indexing model from the issue text.